A synchronous memory device operates in synchronization with a clock to improve the operation speed of a semiconductor memory device. An SDR (single data rate) synchronous memory device inputs/outputs one data in one clock cycle through one data pin in synchronization with a rising edge of a clock. However, the SDR synchronous memory device is insufficient to satisfy the speed requirement of a system performing a high-speed operation. Therefore, a DDR (Double Data Rate) synchronous memory device processing two data in one clock cycle is being used.
The DDR synchronous memory device inputs/outputs two consecutive data through each data input/output pin in synchronization with a rising edge and a falling edge of an external clock. Thus, the DDR synchronous memory device can implement at least two times larger bandwidth than the SDR synchronous memory device, thus making it possible to implement a higher-speed operation.
As the operation speed of semiconductor memory devices increases, the swing width of an interface signal, which is transmitted between the semiconductor memory devices or between the semiconductor memory device and a memory controller, decreases gradually. As the swing width of the interface signal decreases, the influence on an external noise increases and the signal reflection caused by impedance mismatching at an interface terminal becomes serious. The impedance mismatching may make high-speed signal transmission difficult and may distort data outputted from an output terminal of the semiconductor memory device.
Thus, a semiconductor memory device operating at a high speed may include an impedance matching circuit called an ODT (On Die Termination). In general, the ODT performs a source termination at a transmitting terminal by an output circuit, and performs a parallel termination at a receiving terminal by a termination circuit that is connected in parallel to a receiving circuit connected to an input pad.
The resistance value of an ODT varies according to the PVT (Process, Voltage and Temperature) conditions. Thus, a semiconductor memory device includes an impedance calibration circuit that performs a ZQ calibration operation by an external resistor to calibrate the changed resistance value of the ODT.
FIG. 1 is a diagram illustrating a structure of a known impedance calibration circuit.
Referring to FIG. 1, a known impedance calibration circuit includes a pad 11 to which an external resistor R is connected, comparators 12 and 16, counters 13 and 17, pull-up units 14 and 15, and a pull-down unit 18.
Referring to FIG. 1, the comparator 12 compares a pad voltage ZQ with a reference voltage VREF and drives the counter 13 that counts a pull-up code PCODE<1:N> to equalize the resistance of the pull-up units 14 and 15 to the resistance of the external resistor R. When the resistance of the pull-up units 14 and 15 is equalized to the resistance of the external resistor R by the pull-up code PCODE<1:N> counted by the counter 13, the counter 13 stops operating.
The comparator 16 compares a voltage of a node nd10 with the reference voltage VREF and drives the counter 17 that counts a pull-down code NCODE<1:N> to equalize the resistance of the pull-down unit 18 to the resistance of the pull-up unit 15. When the resistance of the pull-down unit 18 is equalized to the resistance of the pull-up unit 15 by the pull-down code NCODE<1:N> counted outputted by the counter 17, the counter 17 stops operating.
As described above, the known impedance calibration circuit equalizes the resistance of the pull-up units 14 and 15 to the resistance of the external resistor R and then equalizes the resistance of the pull-down unit 18 to the resistance of the pull-up unit 15. That is, the known impedance calibration circuit equalizes the resistance of the pull-up units 14 and 15 and the pull-down unit 18 to the resistance of the external resistor R according to a PVT condition change.
However, there may be a ‘calibration range over’ phenomenon that makes it impossible to equalize the resistance of the pull-up units 14 and 15 and the pull-down unit 18 to the resistance of the external resistor R. The calibration range over phenomenon may include a case where the resistance of the pull-up units 14 and 15 cannot be equalized to the resistance of the external resistor R even by the counting of the pull-up code PCODE<1:N> and a case where the resistance of the pull-down unit 18 cannot be equalized to the resistance of the pull-up unit 15 even by the counting of the pull-down code NCODE<1:N>.
If the resistance of the pull-up units 14 and 15 cannot be equalized to the resistance of the external resistor R, the pull-down code NCODE<1:N> is counted by the pull-up unit 15 whose resistance is calibrated by a pull-up code PCODE<1:N> of which counting is completed (e.g., when the pull-up code PCODE<1:N> has highest value). In this case, the resistance of the pull-down unit 18 is equalized to the resistance of the pull-up unit 15.
However, if the resistance of the pull-down unit 18 cannot be equalized to the resistance of the pull-up unit 15 even by the counting of the pull-down code NCODE<1:N>, the pull-up code PCODE<1:N> cannot be again counted. In this case, the operation of the impedance calibration circuit may be terminated without equalizing the resistance of the pull-down unit 18 to the resistance of the pull-up unit 15.